The present invention relates to a semiconductor device and a manufacturing method thereof and in particular to a semiconductor device including a field-effect transistor and a manufacturing method thereof.
Conceivable examples of a semiconductor device including a flash memory or central processing unit (CPU) include microcomputers. A microcomputer generally has a structure having many metal oxide semiconductor (MOS) transistors formed on a semiconductor substrate.
A preferred example of a flash memory is a non-volatile memory, which is a device that retains recorded information even when turned off. A logic circuit such as a CPU is preferably a complementary metal oxide semiconductor (CMOS) transistor, a combination of so-called n-channel and p-channel MOS transistors. Examples of a non-volatile memory include a transistor according to metal oxide nitride oxide silicon (MONOS) technology disclosed in Japanese Unexamined Patent Application Publication No. 2008-41832. Herein, a memory cell according to MONOS technology which is used as a flash memory is referred to as an FMONOS (flash metal oxide nitride oxide semiconductor) memory cell. By forming FMONOS-type memory cells and CMOS transistors on a semiconductor substrate, a high-functionality microcomputer is formed. Such a microcomputer is used in industrial machines, household electrical appliances, car-mounted systems, and the like.
Meanwhile, a technology for increasing the drive current flowing between the source and drain of n-channel and p-channel MOS transistors forming a CMOS transistor is disclosed in X. CHEN, S. FANG et al, “Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45 nm Technology and Beyond,” 2006 Symposium on VLSI Technology Digest of Technical Papers, United States, 2006 IEEE, 2006, 1-4244-0005-8/06/$20.00. This literature discloses a technology called “stress proximity technique (SPT),” that is, a technology that forms a thin film for applying stress to the channel regions of n-channel and p-channel MOS transistors in a manner to cover the MOS transistors. This literature also states that, in the MOS transistors according to the SPT, elimination of a side wall insulating film of a gate electrode increases stress applied to the channel region by the thin film.